1. Field of the Invention
The present invention generally relates to a method of producing simulation models and a simulator using the simulation models.
2. Description of the Related Art
Large-scaled circuits are automatically designed by use of automatic designing apparatuses. Designing flows of the automatic designing apparatuses contain a process of rewriting the highest level description into the lowest level description such as a RT (register transfer) level description. In the highest level description, a desirable operation flow is described by use of a general purpose programming language such as the C language, or an exclusively used operation level description language. In the lowest level description, the desirable operation flow is described by use of a hardware description using hardware resources such as a register and an adder. As illustrated in FIGS. 1A and 1B, in an operation level simulation model 101 having a higher abstract degree, a simulation is carried out based on only an operation simulation model 101 from the beginning to the end. The simulation on the basis of an RT level simulation model 102 cannot be performed during the simulation on the basis of the operation level simulation model 101. Similarly, in the RT level simulation model 102 having a lower abstract degree, the simulation on the basis of only the RT level simulation model 102 is carried out from the beginning to the end. The simulation on the basis of the operation level simulation model 101 cannot be carried out during the simulation on the basis of the RT level simulation model 102. In this way, the simulations of a plurality of simulation models having different abstract degrees from each other cannot be carried out simultaneously.
In this way, the operation level simulation model 101 and the RT level simulation model 102 are handled independently from each other, so that it is impossible to switch from one simulation to another simulation during the simulation. In general, the highest simulation model is used when the simulation speed is an important aspect, whereas the RT level simulation model is used when accuracy is an important aspect. When further higher accuracy is required, another lowest simulation model is used.
However, when a simulation of a function verification is carried out, there is a case that the simulation state from a certain time xe2x80x9ct1xe2x80x9d to another time xe2x80x9ct2xe2x80x9d should be analyzed in detail. In such a case, when the higher accuracy simulator is used for analysis of the simulation state from the time xe2x80x9ct0xe2x80x9d to the time xe2x80x9ct2xe2x80x9d, lengthy time would be required for the simulation.
As the technique capable of solving such a problem, a mixed simulation technique is known from Japanese Laid Open Patent Application (JP-A-Heisei 5-61934) and the publication entitled xe2x80x9cPARALLEL LOGIC SIMULATOR WIZDOMxe2x80x9d (Japanese Information Processing Society, No. 57, Conference held in 1998). In this mixed simulation technique, the simulation is switched between a plurality of simulation models having different abstract degrees from each other such as an instruction level simulation model and an RT level simulation model. Since both of the instruction level simulation model and the RT level simulation model use common structures such as a register, the switching between the instruction level simulation model and the RT level simulation mode is possible.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 7-110826) discloses the technique capable of switching between the simulation in a gate level model and the simulation in an electronic circuit level model. This simulation switching operation is accomplished based on the fact that the terminal of the gate circuit corresponds to the terminal of the electronic circuit.
On the other hand, Japanese Laid Open Patent Application (JP-A-Heisei 10-261002) discloses a simulation switching operation. In this reference, a circuit operation of the circuit is described in a fine definition model and a coarse definition model using a circuit description.
In this way, the above conventional simulation switching operations are known between the higher level model and the lower level model, and between the models having the same levels using the common description, although the fine degrees of the models are different form each other.
However, a highest program language description level as an operation description levelxe2x80x9d and an RT level as a lower description level are not same in the structure for holding the simulation states. For this reason, no data can be transferred between the highest program language description level model and the RT level model. Therefore, conventionally, the simulations cannot be switched between these models. Thus, a technique is required to allow the simulation model between which are not described in a one-to-one correspondence relationship to be switched.
The technique for such requirement is disclosed in copending U.S. patent application Ser. No. 09/517,604 filed on Mar. 2, 2000 and entitled xe2x80x9cLOGIC SIMULATION METHOD IN WHICH SIMULATION IS SWITCHABLE BETWEEN MODELS AND SYSTEM FOR THE SAMExe2x80x9d by the inventor of the present invention. The disclosure of the above application is incorporated herein by the reference.
The inventor found the necessity of a model having an intermediate level between the algorithm description level and an RT level.
Therefore, an object of the present invention is to provide a method of produce simulation models described by a language of an algorithm level having higher abstract degree, a language of an RT level having a lower abstract degree, and a language of an intermediate level between the algorithm level and the RT level.
Another object of the present invention is to provide a simulator which can provide a simulation result in more higher accuracy than the algorithm level simulation and at a higher speed than the RT level simulation.
In an aspect of the present invention, a simulation model producing method is attained by decomposing a total function of an algorithm description model into functions; by scheduling the functions based on clocks in units of groups of allowable status transitions of variables related to the algorithm description model; by allocating resources to each of the scheduled functions under constraint condition of the resources; and by assembling the functions to produce a clock level simulation model.
Here, the simulation model producing method may further include producing a hardware level simulation model based on the resources. In this case, a simulation time of the clock level simulation model is shorter than that of the hardware level simulation model and longer than that of the algorithm description model.
Also, the allocation may be attained by producing a FSM/datapath model based on the functions; and by producing a table indicating correspondence relationship between variables to the algorithm description model and the resources in units of the clocks. In this case, the assembling may include producing the hardware level simulation model based on the table, the FSM/datapath model, and a model interface data.
In order to achieve another aspect of the present invention, a simulation system includes a display, a model producing section and a first simulator. The model producing section produces a clock level simulation model and a first table from an algorithm description model and model interface data indicative of input and output of variables related to the algorithm description model. The clock level simulation model is used for simulating operations of resources in units of groups of allowable status transitions of the variables under constraint condition of the resources. The first table indicating correspondence relationship between the variables and the resources in units of status positions. The first simulator carries out the simulation of the algorithm description model to output variable values in each of the status positions.
Here, the simulation system may further include a control unit which refers to the first table based on the each status position and the variable values to control the display to display resource values for the resources in units of the status positions. Also, the model producing section may further produce a second table from the algorithm description model and the model interface data. The second table indicates correspondence relationship between each of source lines of the algorithm model and a status position.
Also, the simulation system may further include a control unit which refers to the second table based on the each status position to control the display to display the source line for each of the status positions.
Also, the model producing section may further produce a hardware level simulation model from the algorithm description model and the model interface data, the hardware level simulation model being used for simulating the operations of the resources in units of the resources. At this time, the simulation system may further includes: a second simulator carrying out the simulation of the algorithm description model; and a third simulator carrying out the simulation of the hardware level simulation model. In this case, a simulation time of the clock level simulation model is shorter than that of the hardware level simulation model and longer than that of the algorithm description model.
Also, the control unit may carry out simulation while switching between the first to third simulators in response to a switching request.
Also, the variable includes variables expressed in the algorithm description model and temporary variables used in the simulation.
Also, the model producing section decomposes a total function of the algorithm description model into functions, schedules the functions based on clocks in units of groups of allowable status transitions of variables related to the algorithm description model, allocating resources to each of the scheduled functions under constraint condition of the resources and assembles the functions to produce the clock level simulation model.
Also, the model producing section produces an FSM/datapath model based on the algorithm description model and the model interface data, and produces the clock level simulation model from the FSM/datapath model, the model interface data, and the first table.
In still another aspect, a simulation method is attained by producing a clock level simulation model and a first table from an algorithm description model and model interface data indicative of input and output of variables related to the algorithm description model, the clock level simulation model being used for simulating operations of resources in units of groups of allowable status transitions of the variables under constraint condition of the resources, and the first table indicating correspondence relationship between the variables and the resources in units of status positions; and by carrying out the simulation of the algorithm description model to output variable values in each of the status positions.
Here, the simulation method may further include: referring to the first table based on the each status position and the variable values to control a display unit to display resource values for the resources in units of the status positions.
Also, the simulation method may further include: producing a second table from the algorithm description model and the model interface data, the second table indicating correspondence relationship between each of source lines of the algorithm model and a status position; and referring to the second table based on the each status position to control a display unit to display the source line for each of the status positions.
Also, the simulation method may further include: producing a hardware level simulation model from the algorithm description model and the model interface data, the hardware level simulation model being used for simulating the operations of the resources in units of the resources; carrying out the simulation of the algorithm description model; and carrying out the simulation of the hardware level simulation model. In this case, the simulation method may further include: carrying out the simulation while switching between the first to third simulators in response to a switching request.
Also, a simulation time of the clock level simulation model is shorter than that of the hardware level simulation model and longer than that of the algorithm description model.
Also, the variable includes variables expressed in the algorithm description model and temporary variables used in the simulation.
Also, the production may be attained by decomposing a total function of the algorithm description model into functions; by scheduling the functions based on clocks in units of groups of allowable status transitions of variables related to the algorithm description model; by allocating resources to each of the scheduled functions under constraint condition of the resources; and by assembling the functions to produce the clock level simulation model.
Also, the production may be attained by producing a FSM/datapath model based on the algorithm description model and the model interface data; and by producing the clock level simulation model from the FSM/datapath model, the model interface data, and the first table.
In order to achieve yet still another aspect of the present invention, a recording medium is provided in which a program for a simulation method is stored. The simulation method is attained by producing a clock level simulation model and a first table from an algorithm description model and model interface data indicative of input and output of variables related to the algorithm description model, the clock level simulation model being used for simulating operations of resources in units of groups of allowable status transitions of the variables under constraint condition of the resources, and the first table indicating correspondence relationship between the variables and the resources in units of status positions; and by carrying out the simulation of the algorithm description model to output variable values in each of the status positions.